f



'make' rules

Hi,
I would like to configure my makefile so that the executables/object
files are created in another directory rather than the current
directory, i.e.
src: is the directory where I have src. code and makefile
I want the exes and object files in
.../obj

Is this possible?
Thanks.

0
1/16/2007 1:42:46 AM
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"psp" <pradhan.pushkar@gmail.com> wrote in message 
news:1168911766.655169.245230@38g2000cwa.googlegroups.com...
> Hi,
> I would like to configure my makefile so that the executables/object
> files are created in another directory rather than the current
> directory, i.e.
> src: is the directory where I have src. code and makefile
> I want the exes and object files in
> ../obj

The most straightforward way to do this would seem to be to write the rules 
so that the compiler simply plops them in that directory, i.e.

gcc -o ../obj/cookiemonster.o cookiemonster.c

Of course, you need to be sure the directory exists first.

What level of sophistication are you operating at with your makefile (i.e. 
explicit rules, implicit rules, etc.?).  It might help to post your 
makefile.

Dave.

-- 
David T. Ashley              (dta@e3ft.com)
http://www.e3ft.com          (Consulting Home Page)
http://www.dtashley.com      (Personal Home Page)
http://gpl.e3ft.com          (GPL Publications and Projects) 


0
dta (455)
1/16/2007 4:24:55 AM
David T. Ashley wrote:
> "psp" <pradhan.pushkar@gmail.com> wrote in message
> news:1168911766.655169.245230@38g2000cwa.googlegroups.com...
> > Hi,
> > I would like to configure my makefile so that the executables/object
> > files are created in another directory rather than the current
> > directory, i.e.
> > src: is the directory where I have src. code and makefile
> > I want the exes and object files in
> > ../obj
>
> The most straightforward way to do this would seem to be to write the rules
> so that the compiler simply plops them in that directory, i.e.
>
> gcc -o ../obj/cookiemonster.o cookiemonster.c
>
> Of course, you need to be sure the directory exists first.
>
> What level of sophistication are you operating at with your makefile (i.e.
> explicit rules, implicit rules, etc.?).  It might help to post your
> makefile.
>
> Dave.

That's what I tried through my makefile, below is my makefile:

..NO_PARALLEL:
..KEEP_STATE:

..SUFFIXES:
..SUFFIXES: .cpp $(SUFFIXES)

TOP_SRC=/xxx
OBJ=../obj

IPC_INC   = $(TOP_PROJ)/sub/dap/ipc/pub

UTIL_INC = $(TOP_PROJ)/lib/util/pub

INCLUDE=-I$(IPC_INC)\
	-I$(UTIL_INC)

CCFLAGS = $(INCLUDE) $(STD_PDI_CC_OPTS) -c -g

SOCKOBJS = $(OBJ)/PDSockComm.o

IPCOBJS = $(OBJ)/PDDaqQueue.o

SOCKLIB=$(OBJ)/libcomm.a
IPCLIB=$(OBJ)/libipc.a

all: $(SOCKLIB) $(IPCLIB)

$(SOCKLIB): $(SOCKOBJS) Makefile
	rm -f $(SOCKLIB)
	ar rcv $(SOCKLIB) $(SOCKOBJS)

$(IPCLIB): $(IPCOBJS) Makefile
	rm -f $(IPCLIB)
	ar rcv $(IPCLIB) $(IPCOBJS)

clean:
	rm -f $(OBJ)/*.o $(SOCKLIB) $(IPCLIB)

0
1/16/2007 5:31:38 PM
psp wrote:
> David T. Ashley wrote:
> > "psp" <pradhan.pushkar@gmail.com> wrote in message
> > news:1168911766.655169.245230@38g2000cwa.googlegroups.com...
> > > Hi,
> > > I would like to configure my makefile so that the executables/object
> > > files are created in another directory rather than the current
> > > directory, i.e.
> > > src: is the directory where I have src. code and makefile
> > > I want the exes and object files in
> > > ../obj
> >
> > The most straightforward way to do this would seem to be to write the rules
> > so that the compiler simply plops them in that directory, i.e.
> >
> > gcc -o ../obj/cookiemonster.o cookiemonster.c
> >
> > Of course, you need to be sure the directory exists first.
> >
> > What level of sophistication are you operating at with your makefile (i.e.
> > explicit rules, implicit rules, etc.?).  It might help to post your
> > makefile.
> >
> > Dave.
>
> That's what I tried through my makefile, below is my makefile:
>
> .NO_PARALLEL:
> .KEEP_STATE:
>
> .SUFFIXES:
> .SUFFIXES: .cpp $(SUFFIXES)
>
> TOP_SRC=/xxx
> OBJ=../obj
>
> IPC_INC   = $(TOP_PROJ)/sub/dap/ipc/pub
>
> UTIL_INC = $(TOP_PROJ)/lib/util/pub
>
> INCLUDE=-I$(IPC_INC)\
> 	-I$(UTIL_INC)
>
> CCFLAGS = $(INCLUDE) $(STD_PDI_CC_OPTS) -c -g
>
> SOCKOBJS = $(OBJ)/PDSockComm.o
>
> IPCOBJS = $(OBJ)/PDDaqQueue.o
>
> SOCKLIB=$(OBJ)/libcomm.a
> IPCLIB=$(OBJ)/libipc.a
>
> all: $(SOCKLIB) $(IPCLIB)
>
> $(SOCKLIB): $(SOCKOBJS) Makefile
> 	rm -f $(SOCKLIB)
> 	ar rcv $(SOCKLIB) $(SOCKOBJS)
>
> $(IPCLIB): $(IPCOBJS) Makefile
> 	rm -f $(IPCLIB)
> 	ar rcv $(IPCLIB) $(IPCOBJS)
>
> clean:
> 	rm -f $(OBJ)/*.o $(SOCKLIB) $(IPCLIB)

In this situation you can provide for separation of the source and
object files using a pattern rule,

$(OBJ)/%.o: $(SRCDIR)/%.cpp
    $(CXX) -o $@ $< $(CCFLAGS)

(It's not clear from the above what your source directory is, so I've
invented a variable SRCDIR.)

0
toby23 (1177)
1/16/2007 5:52:57 PM
toby wrote:
> psp wrote:
> > David T. Ashley wrote:
> > > "psp" <pradhan.pushkar@gmail.com> wrote in message
> > > news:1168911766.655169.245230@38g2000cwa.googlegroups.com...
> > > > Hi,
> > > > I would like to configure my makefile so that the executables/object
> > > > files are created in another directory rather than the current
> > > > directory, i.e.
> > > > src: is the directory where I have src. code and makefile
> > > > I want the exes and object files in
> > > > ../obj
> > >...
> In this situation you can provide for separation of the source and
> object files using a pattern rule,
>
> $(OBJ)/%.o: $(SRCDIR)/%.cpp
>     $(CXX) -o $@ $< $(CCFLAGS)
>
> (It's not clear from the above what your source directory is, so I've
> invented a variable SRCDIR.)

I should add, if you want *multiple* source directories, use vpath and
a different pattern rule, e.g.:

vpath %.cpp src1 src2  # name your source directories here
%.o: %.cpp
    $(CXX) -o $@ $< $(CCFLAGS)

Dependencies still reference $(OBJ)/xx.o, etc., but make will search
the vpath directories for the corresponding source file.

0
toby23 (1177)
1/16/2007 5:57:37 PM
toby wrote:
> psp wrote:
> > David T. Ashley wrote:
> > > "psp" <pradhan.pushkar@gmail.com> wrote in message
> > > news:1168911766.655169.245230@38g2000cwa.googlegroups.com...
> > > > Hi,
> > > > I would like to configure my makefile so that the executables/object
> > > > files are created in another directory rather than the current
> > > > directory, i.e.
> > > > src: is the directory where I have src. code and makefile
> > > > I want the exes and object files in
> > > > ../obj
> > >
> > > The most straightforward way to do this would seem to be to write the rules
> > > so that the compiler simply plops them in that directory, i.e.
> > >
> > > gcc -o ../obj/cookiemonster.o cookiemonster.c
> > >
> > > Of course, you need to be sure the directory exists first.
> > >
> > > What level of sophistication are you operating at with your makefile (i.e.
> > > explicit rules, implicit rules, etc.?).  It might help to post your
> > > makefile.
> > >
> > > Dave.
> >
> > That's what I tried through my makefile, below is my makefile:
> >
> > .NO_PARALLEL:
> > .KEEP_STATE:
> >
> > .SUFFIXES:
> > .SUFFIXES: .cpp $(SUFFIXES)
> >
> > TOP_SRC=/xxx
> > OBJ=../obj
> >
> > IPC_INC   = $(TOP_PROJ)/sub/dap/ipc/pub
> >
> > UTIL_INC = $(TOP_PROJ)/lib/util/pub
> >
> > INCLUDE=-I$(IPC_INC)\
> > 	-I$(UTIL_INC)
> >
> > CCFLAGS = $(INCLUDE) $(STD_PDI_CC_OPTS) -c -g
> >
> > SOCKOBJS = $(OBJ)/PDSockComm.o
> >
> > IPCOBJS = $(OBJ)/PDDaqQueue.o
> >
> > SOCKLIB=$(OBJ)/libcomm.a
> > IPCLIB=$(OBJ)/libipc.a
> >
> > all: $(SOCKLIB) $(IPCLIB)
> >
> > $(SOCKLIB): $(SOCKOBJS) Makefile
> > 	rm -f $(SOCKLIB)
> > 	ar rcv $(SOCKLIB) $(SOCKOBJS)
> >
> > $(IPCLIB): $(IPCOBJS) Makefile
> > 	rm -f $(IPCLIB)
> > 	ar rcv $(IPCLIB) $(IPCOBJS)
> >
> > clean:
> > 	rm -f $(OBJ)/*.o $(SOCKLIB) $(IPCLIB)
>
> In this situation you can provide for separation of the source and
> object files using a pattern rule,
>
> $(OBJ)/%.o: $(SRCDIR)/%.cpp
>     $(CXX) -o $@ $< $(CCFLAGS)
>
> (It's not clear from the above what your source directory is, so I've
> invented a variable SRCDIR.)

Thanks it worked, I replaced $(CXX) with $(CCC) i.e. my CC compiler.
Although I read the man page of make I can't understand  $(CXX) -o $@
$< $(CCFLAGS).
Will $@ be each of the .o file and $< the .cc file on which it depends?

0
1/16/2007 7:17:58 PM
psp wrote:
> toby wrote:
> > psp wrote:
> > > David T. Ashley wrote:
> > > > "psp" <pradhan.pushkar@gmail.com> wrote in message
> > > > news:1168911766.655169.245230@38g2000cwa.googlegroups.com...
> > > > > Hi,
> > > > > I would like to configure my makefile so that the executables/object
> > > > > files are created in another directory rather than the current
> > > > > directory, ...
> >
> > In this situation you can provide for separation of the source and
> > object files using a pattern rule,
> >
> > $(OBJ)/%.o: $(SRCDIR)/%.cpp
> >     $(CXX) -o $@ $< $(CCFLAGS)
> >
> > (It's not clear from the above what your source directory is, so I've
> > invented a variable SRCDIR.)
>
> Thanks it worked, I replaced $(CXX) with $(CCC) i.e. my CC compiler.

$(CXX) means the system's C++ compiler. Other conventional flags (as
used by make's built-in rules) are $(CPPFLAGS) for preprocessor flags
and $(CXXFLAGS) for C++ compile flags.

> Although I read the man page of make I can't understand  $(CXX) -o $@
> $< $(CCFLAGS).
> Will $@ be each of the .o file and $< the .cc file on which it depends?

Yes - clearly explained in the GNU make manual (or 'info make').

0
toby23 (1177)
1/16/2007 8:05:41 PM
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