Hi,

I'm using a make program similar to gnu make.  I'd like to always
recompile a file whenever ANY file is compiled (or assembled).
Preferably (but not absolutely necessary), I'd like the file to
recompile if the linker runs as well, but this sounds really tough.
In case you're wondering, this file contains a global array that has
time and date stamp information in it so we can tell when the project
was last built.

Some engineers don't like a simple "delete the object file always when
make runs" approach because if you inadvertently run make a second
time, you get a recompile even if no sources changed.

Any ideas on how to do this?


Thanks much,


Jim

Jim wrote:
> Hi,
> 
> I'm using a make program similar to gnu make.  I'd like to always
> recompile a file whenever ANY file is compiled (or assembled).
> Preferably (but not absolutely necessary), I'd like the file to
> recompile if the linker runs as well, but this sounds really tough.
> In case you're wondering, this file contains a global array that has
> time and date stamp information in it so we can tell when the project
> was last built.
> 
> Some engineers don't like a simple "delete the object file always when
> make runs" approach because if you inadvertently run make a second
> time, you get a recompile even if no sources changed.
> 
> Any ideas on how to do this?

     Maybe you could find half a dozen more newsgroups to ask?

     A first cut might be to put the recompile *in* the link
step, unconditionally, along the lines of (sketch)

	OBJECTS = ... everything *except* timestamp.o ...
	target: $(OBJECTS)
		cc $(CFLAGS) -o target timestamp.c $(OBJECTS)

If you run make twice and it sees that target is up to date
(note that timestamp.c doesn't count toward that decision), it
will not run the link step and will not recompile timestamp.c.

-- 
Eric Sosman
esosman@ieee-dot-org.invalid

Jim <james.ro123@yahoo.com> writes:

>I'm using a make program similar to gnu make.  I'd like to always
>recompile a file whenever ANY file is compiled (or assembled).
>Preferably (but not absolutely necessary), I'd like the file to
>recompile if the linker runs as well, but this sounds really tough.
>In case you're wondering, this file contains a global array that has
>time and date stamp information in it so we can tell when the project
>was last built.

>Some engineers don't like a simple "delete the object file always when
>make runs" approach because if you inadvertently run make a second
>time, you get a recompile even if no sources changed.

As I'm sure you know, compiling the date into the program is the easy
part.  In my Makefile I add these actions to the primary target:

	@rm -f lastmod.c
	@date '+char *LASTMODIFIED = "%l:%M%P %b %d %Y";' > lastmod.c
	@$(CC) $(CFLAGS) -c lastmod.c

I have lastmod.c as one of the dependencies of my final target, so the
above is only executed and compiled (before linking) if any other the
other source file will also require compiling.

-- 
Chris.

Jim <james.ro123@yahoo.com> wrote:
> Hi,
>=20
> I'm using a make program similar to gnu make.  I'd like to always
> recompile a file whenever ANY file is compiled (or assembled).
> Preferably (but not absolutely necessary), I'd like the file to
> recompile if the linker runs as well, but this sounds really tough.

So, it means that any object or executable file depends on this target.
Assuming you've macros OBJS and EXES containing a list of object files and =
executable files, this should look like:

$(OBJS) $(EXES): your_compiled_file
your_compiled_file:
	your command line

--=20
Andr=C3=A9 Gillibert

>I'm using a make program similar to gnu make.  I'd like to always
>recompile a file whenever ANY file is compiled (or assembled).
>Preferably (but not absolutely necessary), I'd like the file to
>recompile if the linker runs as well, but this sounds really tough.

I'm not sure I understand your requirements, but here is one way to
do it which I think meets them:

	Change the entry for the link step, so it always
compiles the global array.:

foo:	foo1.o foo2.o ... global_array.o
	cc -o foo foo1.o foo2.o .. global_array.o -lfoo -lbar

to:

foo:	foo1.o foo2.o ... global_array.c
	cc -c global_array.c
	cc -o foo foo1.o foo2.o .. global_array.o -lfoo -lbar

I presume it is not important to recompile global_array if you
recompile pieces of the program *WITHOUT* linking as you didn't
rebuild the whole thing, and it will be recompiled when you do
a full build.

>In case you're wondering, this file contains a global array that has
>time and date stamp information in it so we can tell when the project
>was last built.

>Some engineers don't like a simple "delete the object file always when
>make runs" approach because if you inadvertently run make a second
>time, you get a recompile even if no sources changed.

On Wed, 26 Aug 2009 14:02:39 -0700 (PDT)
Jim <james.ro123@yahoo.com> wrote:

> I'm using a make program similar to gnu make.  I'd like to always
> recompile a file whenever ANY file is compiled (or assembled).

	One way which should work with any make is to have the object in
question depend on all source files even though the action only refers to
one of them.

-- 
Steve O'Hara-Smith                          |   Directable Mirror Arrays
C:>WIN                                      | A better way to focus the sun
The computer obeys and wins.                |    licences available see
You lose and Bill collects.                 |    http://www.sohara.org/

Jim <james.ro123@yahoo.com> writes:
>Hi,
>
>I'm using a make program similar to gnu make.  I'd like to always
>recompile a file whenever ANY file is compiled (or assembled).
>Preferably (but not absolutely necessary), I'd like the file to
>recompile if the linker runs as well, but this sounds really tough.
>In case you're wondering, this file contains a global array that has
>time and date stamp information in it so we can tell when the project
>was last built.
>
>Some engineers don't like a simple "delete the object file always when
>make runs" approach because if you inadvertently run make a second
>time, you get a recompile even if no sources changed.
>
>Any ideas on how to do this?
>

 ...


all:    $(TARGET)

$(TARGET): vsim_built buildsubs $(OBJECTS) $(SIM_LIBS)
        $(CXX) $(DEBUGFLAGS) $(LDFLAGS) -o $@ $(OBJECTS) $(SIM_LIBS) $(HOST_LIBS)


..PHONY: vsim_built
vsim_built:
        @echo " VSIM_BUILT"
        @echo "static const char *vsim_built = \"VSIM built on $$(uname -n)\n           by $$(id -un)\n           at $$(date +"%Y-%m-%d %H:%M")\n           from $$(pwd)\n           using $(CXXFLAGS)\";" > include/built.h
        @echo "static const unsigned int VSIM_VERSION_MAJOR=$(VSIM_VERS_MAJ);" >> include/built.h
        @echo "static const unsigned int VSIM_VERSION_MINOR=$(VSIM_VERS_MIN);" >> include/built.h
        @echo "static const unsigned int VSIM_BUILD_NUMBER=$(VSIM_BUILD_NUM);" >> include/built.h

if you use dependencies (makedepend or gcc built-in), the dependency on built.h will be
automatically picked up on every make.

scott

Jim <james.ro123@yahoo.com> writes:
> I'm using a make program similar to gnu make.  I'd like to always
> recompile a file whenever ANY file is compiled (or assembled).
> Preferably (but not absolutely necessary), I'd like the file to
> recompile if the linker runs as well, but this sounds really tough.

This is actually really simple: Use a wrapper-script which recompiles
the file and then invokes either the compiler or the linker. Should
you be using gcc, one script should be sufficient.

On Aug 26, 5:02=A0pm, Jim <james.ro...@yahoo.com> wrote:
> Hi,
>
> I'm using a make program similar to gnu make. =A0I'd like to always
> recompile a file whenever ANY file is compiled (or assembled).
> Preferably (but not absolutely necessary), I'd like the file to
> recompile if the linker runs as well, but this sounds really tough.
> In case you're wondering, this file contains a global array that has
> time and date stamp information in it so we can tell when the project
> was last built.
>
> Some engineers don't like a simple "delete the object file always when
> make runs" approach because if you inadvertently run make a second
> time, you get a recompile even if no sources changed.
>
> Any ideas on how to do this?
>
> Thanks much,
>
> Jim

I'd like to thank everyone for you input!  Now, for the sake of
discussion, I'd like to change the requirements a bit.  I really don't
need this, but it may come in handy:

I'd like to have a variable, say COMPILE_ALWAYS, set to a file that
needs to be compiled/assembled always.  This file may be a .c, .cpp or
an assembler file.  So, the methods I've seen here that involve
writing the ruleset for that file just won't do because now you don't
know what file you'll be building.  How would you go about doing it?
My current thought is to place a line where the linking is done
(before the link itself) that recursively calls make--it's target
would be $(COMPILE_ALWAYS).o.  Comments?

Thanks again,


Jim

Jim <james.ro123@yahoo.com> writes:
> On Aug 26, 5:02�pm, Jim <james.ro...@yahoo.com> wrote:
>> Hi,
>>
>> I'm using a make program similar to gnu make. �I'd like to always
>> recompile a file whenever ANY file is compiled (or assembled).
>> Preferably (but not absolutely necessary), I'd like the file to
>> recompile if the linker runs as well, but this sounds really tough.
>> In case you're wondering, this file contains a global array that has
>> time and date stamp information in it so we can tell when the project
>> was last built.
>>
>> Some engineers don't like a simple "delete the object file always when
>> make runs" approach because if you inadvertently run make a second
>> time, you get a recompile even if no sources changed.
>>
>> Any ideas on how to do this?
>>
>> Thanks much,
>>
>> Jim
>
> I'd like to thank everyone for you input!  Now, for the sake of
> discussion, I'd like to change the requirements a bit.  I really don't
> need this, but it may come in handy:
>
> I'd like to have a variable, say COMPILE_ALWAYS, set to a file that
> needs to be compiled/assembled always.  This file may be a .c, .cpp or
> an assembler file.  So, the methods I've seen here that involve
> writing the ruleset for that file just won't do because now you don't
> know what file you'll be building.  How would you go about doing it?

Use a .PHONY target as prerequisite of the 'build' target, put the
variable (expansion) inside the compilation rule instead of the
filename, use a wrapper script and pass the variable expansion as
argument, ...

> My current thought is to place a line where the linking is done
> (before the link itself) that recursively calls make--it's target
> would be $(COMPILE_ALWAYS).o.  Comments?

You really don't want a comment on this idea :->>.