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comp.lang.vhdl

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Top Articles in comp.lang.vhdl

Help! Signed Number Representation in Xilinx Testbench Waveform

929 (1/18/2006 6:54:19 PM)
Hi, I am using Xilinx ISE Testbench Waveform to simulate my VHDL code and there is something that confused me: -256 is equal to '111100000000' in two's complement notation.'111100000000' is equal to 3840 if y... Report Spam

emeltasyurek (7)

Carry Save Adder (CSA) Verilog code

883 (11/13/2006 12:00:53 PM)
Hi, I need the Verilog code for a carry save adder (CSA). Can some one please supply this. It takes three inputs and produces 2 outputs - the sum and the carry. Thaks Much. ... Report Spam

humble_Stuff (2)

USB NRZI encoding and bit stuffing question

1363 (6/27/2007 2:05:11 PM)
I'm Looking at the USB D+ line with a Tektronix digital storage scope, the connection is from a PC to a fake "USB function" (by pulling up the D+ line with a 1.5k resistor to 3.3V supply, and nothing else). Th... Report Spam

cxu_dl (3)

How to write a VHDL code for 1Hz signal?

694 (1/8/2008 7:31:59 PM)
Hello, I am a newbie to VHDL programming and want to test my FPGA board with a code which lights a LED every second. To do this I need a VHDL code for 1 Hz signal generator. Unfortunately, I cannot find such i... Report Spam

vladimir.v.korostelev (17)

Convert from std_logic_vector to real

1637 (8/4/2005 8:15:58 PM)
Is there a standard library function (e.g., to_real) to convert a std_logic_vector to a real value? If not, how would one go about doing this? ... Report Spam

eNo

converting std_logic_vector to an integer without sign extension

1193 (11/25/2009 2:28:01 PM)
I'm trying to elegantly convert a std_logic_vector(upper downto lower) to an integer without sign extension using ieee.numeric_std with upper and lower taking on values from 31 to 0 and with upper >= lower. ... Report Spam

marmarjohnson (1)

How to extract subarray ?

909 (11/15/2009 3:46:59 AM)
My VHDL is a bit rusty and maybe this is a very silly question. I wish to do the following - suppose I have: A : in std_logic_vector(7 downto 0); How do I extract say bits 3 -> 0 ? Is there any notion of c... Report Spam

dakupoto (39)

binary to integer conversion code

1415 (6/23/2008 5:31:53 AM)
I wrote a simple program to converting 4bit binary to integer and display the same on my 7 segment leds. my program got synthesized and mapped and placed and routed . but when i tried to run this program on my ... Report Spam

Ashani

How to write testbench file?

1212 (1/27/2010 6:18:02 AM)
Hi, i am using an actel fpga to generate pwm signal. There are these IP cores in the libero software for you to drage and drop into your design. I have the following .vhd code and is having a hard time tryin... Report Spam

RaulGonz

VHDL code for multiplier

915 (8/21/2004 2:29:12 AM)
Need help for writing VHDL code for a generic multiplier..Help for Booth and Wallace tree is also looked forward ... Report Spam

chi_rulez