Ralf-Hildebrandt's articles:

Items(5) /1

TMS320C6416 DSK EMIFA 1 29 (7/17/2008 1:25:00 PM) comp.dsp Hi! First of all: This is my 1st project with the TMS320C6416 DSK and I am a rookie with the TMS320. I try to use the EMIFA for communication to a FPGA board (asynchronous memory interface). Unfortunately I... Ralf

configurations and generate 5 55 (9/24/2004 10:07:00 AM) comp.lang.vhdl Hi all! I have to write the configuration for a component, that contains some subcomponents, that are instanced depending on generic parameters. Let me give a theoretical example: architecture behavior of ... Ralf

clocking on a variable 6 75 (6/19/2004 8:17:46 AM) comp.lang.vhdl Hi all! I just want to hear some opinions about the following (illegal) construct: process(sig_A,sig_B) variable clock : std_ulogic; begin clock:=sig_A XOR sig_B; if rising_edge(clock) then -- do something ... Ralf

PIC MSSP module in I2C mode 2 41 (6/16/2004 11:39:19 AM) comp.arch.embedded Hi all! The Microchip PIC16F87XA has got a MSSP module. Bits SSPM(3 downto 0) in SSPCON register configure the mode of the module. For I2C operation the following options are available: 1111 = I2C slave, 1... Ralf

data types (bitwidth) and multiplication 9 32 (12/18/2003 10:34:28 AM) comp.lang.c Hi all! First of all: I am a C-newbie. I have noticed a "strange" behavior with the standart integer multiplication. The code is: void main(void) { int a = 0x1234; int b = 0xABCD; long int result_1 = (... Ralf

Ralf-Hildebrandt's replies:

Items(4) /1

data types (bitwidth) and multiplication 9 32 (12/18/2003 10:34:28 AM) comp.lang.c Hi all! First of all: I am a C-newbie. I have noticed a "strange" behavior with the standart integer multiplication. The code is: void main(void) { int a = 0x1234; int b = 0xABCD; long int result_1 = (... Ralf-Hildebrandt (9)

TMS320C6416 DSK EMIFA 1 29 (7/17/2008 1:25:00 PM) comp.dsp Hi! First of all: This is my 1st project with the TMS320C6416 DSK and I am a rookie with the TMS320. I try to use the EMIFA for communication to a FPGA board (asynchronous memory interface). Unfortunately I... Ralf-Hildebrandt (9)

Check all bits set 10 27 (6/22/2012 4:55:40 PM) comp.lang.vhdl library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; signal WRaddr : unsigned(11 downto 0); if rising_edge(CLK) then if WRaddr/="111111111111" then WRaddr <= WRaddr +1; ... aleksaZR (112)

how to define a type with inputs and outputs like a bus 2 21 (7/23/2012 6:25:27 PM) comp.lang.vhdl I would want to define a bus interface such that I can use it everywhere I need. I get into a trouble is I need to separate the input and output into two types. Is there a way to let it only need to decla... aikenpang (2)