Zorjak's articles:

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Sysgen simulation question 0 164 (9/2/2009 8:26:18 AM) comp.arch.fpga Hello to everyone, I have a question about sysgen simulation. This is the situation. I have design that have two clock domains. one will work on 133MHz and the other will work on 40MHz. from transition from on... Zorjak

Serial Pheripheral Interface for XILINX FPGA 5 152 (7/4/2008 11:13:11 AM) comp.arch.fpga Hi, I have one question if anyone can give me some clues. I need to realize SPI (Serial Pheriferal Interface for my project). Does anybody knows is there any free version of this core that can be foud on the n... Zorjak

XILINX core generator question 4 45 (5/26/2008 2:37:06 PM) comp.arch.fpga Hi, Can someone help me please. I am trying familiarize myself with xilinx ISE an d core generator. I was trying to realize simple "fifo core" using core generator. I have done all the procedure and the core h... Zorjak

xilinx beginner modelsim question 4 39 (5/14/2008 12:09:47 PM) comp.arch.fpga Hi!!! I started recently with the xilinx software and these days I am trying to become more familiar with the modelsim and ise. I wanted to test some basic counter simulation in modelsim so I used this simple... Zorjak

bidirectional pin help 15 77 (8/27/2007 3:51:39 PM) comp.arch.fpga Hi everyone I am working on some FPGA project and I need to define one port as bidirectional. This is my VHDL code --------------------------------------------------------------------------------------------... Zorjak

IIR filter help #2 20 49 (8/10/2007 9:20:16 PM) comp.arch.embedded Hi, I have one question regarding implementation of IIR filter. I try to write C code of IIR filter for ARM microcontroler for real time signal processing. Filter should be lowpass and second order. I try to do... Zorjak

IIR filter help 8 25 (8/10/2007 3:43:30 PM) comp.dsp Hi, I have one question regarding implementation of IIR filter. I try to write C code of IIR filter for ARM microcontroler for real time signal processing. Filter should be lowpass and second order. I try to do... Zorjak

bidirectional pin 7 88 (8/5/2007 7:22:12 PM) comp.arch.fpga Hi, I start work on some project involving FPGA and I have to define port as bidirectional (inut-output). I know that in VHDL there is keyword "inout" when defining port, but I don't know what detirminats that ... Zorjak

Quartus Timing Analyzer question 5 104 (6/14/2007 10:12:39 PM) comp.arch.fpga Hi. I am working with Alera Quartus software on FPGA realization of STFT(Short Time Fourier Transform) and I have one problem. I am constantly getting this waring "Warning: Circuit may not operate. Detected 14... Zorjak

FIR filter generic #2 1 107 (10/19/2006 11:25:12 PM) comp.lang.vhdl Hi. I am trying to write generic VHDL code for FIR filter. generic parametars should be word_length, filter_order. Can anybody help me how to input filter coeficients. I tought something like, read coeficitien... Zorjak

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IIR filter help 8 25 (8/10/2007 3:43:30 PM) comp.dsp Hi, I have one question regarding implementation of IIR filter. I try to write C code of IIR filter for ARM microcontroler for real time signal processing. Filter should be lowpass and second order. I try to do... Zorjak (19)

IIR filter help #2 20 49 (8/10/2007 9:20:16 PM) comp.arch.embedded Hi, I have one question regarding implementation of IIR filter. I try to write C code of IIR filter for ARM microcontroler for real time signal processing. Filter should be lowpass and second order. I try to do... Zorjak (19)