a12345731's articles:

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FPGA circuit simulator 2 210 (4/25/2012 5:14:40 AM) comp.arch.fpga Hi, I wanted to know if there's any simulator like proteus for FPGAs, like where we can have a FPGA interfaced with some other ICs or LCD etc and without implementing it on hardware, we can see the output on si... salimbaba

RPMs in xilinx 13.2 3 76 (4/9/2012 8:53:38 AM) comp.arch.fpga Hi, I am using xilinx 13.2 for synthesis and implementation of my design. I wanted to create RPMs of some small logic so that I can reuse it anywhere in my design by just instantiating. But I cannot find any re... salimbaba

FPGA not working after programming from EEPROM 5 45 (1/26/2012 10:46:39 AM) comp.arch.fpga Hi, I am using xilinx spartan 3 xc3s4000 FPGA in my design interfaced with two gigabit phyters from National and I have xilinx xcf16p EEPROM on board to program the FPGA. When I program the FPGA using JTAG, e... salimbaba

gigabit ethernet problem 16 54 (9/22/2011 7:21:23 PM) comp.arch.fpga Hi, I am using xilinx spartan3 xc3s4000 in my design. It is interfaced with 2 national Gigabit PHYs. So i receive a packet from phy A and transmit it to PHY B and vice versa. Now the problem i am facing is that... salimbaba

LFSR in xilinx 13.2 4 55 (9/15/2011 7:38:33 PM) comp.arch.fpga Hi, I am using xilinx 13.2 for my design synthesis and i want to use xilinx IP for LFSR but i cannot find it in core gen. I am using Spartan3 xc3s4000 FPGA. Does anyone know where i can find it? regards ... salimbaba

interfacing Xilinx platform usb jtag with other vendor devices 3 63 (9/6/2011 1:43:06 PM) comp.arch.fpga is xilinx platform usb jtag supports non-xilinx devices regards salim --------------------------------------- Posted through http://www.FPGARelated.com ... salimbaba

Boundary scan #2 3 47 (8/29/2011 3:42:11 PM) comp.arch.fpga Hi, i wanted to know whether there exists any software that can be used to know whether all the balls of my bga grid are properly fixed in place or not. Actually i am using spartan 3 xc3s4000 and maxim 28544 in... salimbaba

RTL timing issue 3 40 (7/15/2011 1:53:08 PM) comp.arch.fpga Hi, I am using a customized board with 1 spartan 3 xc3s4000 FPGA and 2 Gigabit Phys. My system clock is 125Mhz and i am facing an issue which occurs after a while but since it occurs so it is a problem for me.... salimbaba

FPGA not getting programmed 13 40 (7/14/2011 7:45:40 PM) comp.arch.fpga Hi, I am using a custom board design in which i have 2 FPGAs (spartan 3 xc3s4000) and an EEPROM xcf16p daisy chained together. The chain is like this: EEPROM -> FPGA1 -> FPGA2 Now the problem is that when i t... salimbaba

Ericsson Eurocom D1 0 35 (6/30/2011 7:15:50 PM) comp.arch.fpga Hi, I know this isn't the right place to ask this question, but since i use this forum frequently, i thought i should start from here. Has anybody here worked on Ericsson's Eurocom D1 protocol ? I need some h... salimbaba

a12345731's replies:

Items(10) /1

ping pong buffer overflow issue 6 83 (3/14/2011 6:35:51 PM) comp.arch.fpga Hi, I am working on Gigabit MAC RTL, and i am using spartan3 xc3s4000 in my design. I have a Ping Pong buffer implemented in the pipeline stage, but the problem is that my buffers overflow when i send bursty tr... a12345731 (38)

same RTL on two same boards giving different behaviour 14 29 (4/17/2011 6:06:43 PM) comp.arch.fpga Hi, I am using spartan3 xc3s4000 custom board in my design interfaced with a national PHY DP83865, xilinx 12.3 for synthesis and implementation and i'm facing a strange problem. I run the same RTL on two boards... a12345731 (38)

comparator fast implementation 5 48 (5/23/2011 7:31:38 PM) comp.arch.fpga Hi, In my design i have two counters, a write_counter and a read_counter, both are 11 bits wide. I used a simple compare equation like this: assign last_byte = odd_number_bytes ? (read_counter + 2 == write_cou... a12345731 (38)

ucf file for 32 bit counter spartan 3e S500E -4 2 46 (6/21/2011 11:56:07 AM) comp.arch.fpga I have designed a 32 bit counter but I am having a difficulty in assigning 32 pins to the 32 bits since I don't know the "LOC" (location) of the pins which is required in the User Constraints file. I need help.... hi.maddy08 (1)

Help with bidirectional interface of a FPGA with a uC 4 36 (7/3/2011 12:21:10 AM) comp.arch.fpga Hi need to implement a bidirectional 8 bit interface of a FPGA with a microcontroller. For now i am developing with a Ciclone II but i will have to make it for a Spartan-3A too. Inside the FPGA i have 2 fifos ... sink00278 (28)

FPGA not getting programmed 13 40 (7/14/2011 7:45:40 PM) comp.arch.fpga Hi, I am using a custom board design in which i have 2 FPGAs (spartan 3 xc3s4000) and an EEPROM xcf16p daisy chained together. The chain is like this: EEPROM -> FPGA1 -> FPGA2 Now the problem is that when i t... a12345731 (38)

RTL timing issue 3 40 (7/15/2011 1:53:08 PM) comp.arch.fpga Hi, I am using a customized board with 1 spartan 3 xc3s4000 FPGA and 2 Gigabit Phys. My system clock is 125Mhz and i am facing an issue which occurs after a while but since it occurs so it is a problem for me.... a12345731 (38)

gigabit ethernet problem 16 54 (9/22/2011 7:21:23 PM) comp.arch.fpga Hi, I am using xilinx spartan3 xc3s4000 in my design. It is interfaced with 2 national Gigabit PHYs. So i receive a packet from phy A and transmit it to PHY B and vice versa. Now the problem i am facing is that... a12345731 (38)

FPGA not working after programming from EEPROM 5 45 (1/26/2012 10:46:39 AM) comp.arch.fpga Hi, I am using xilinx spartan 3 xc3s4000 FPGA in my design interfaced with two gigabit phyters from National and I have xilinx xcf16p EEPROM on board to program the FPGA. When I program the FPGA using JTAG, e... a12345731 (38)

RPMs in xilinx 13.2 3 76 (4/9/2012 8:53:38 AM) comp.arch.fpga Hi, I am using xilinx 13.2 for synthesis and implementation of my design. I wanted to create RPMs of some small logic so that I can reuse it anywhere in my design by just instantiating. But I cannot find any re... a12345731 (38)