bradsmallridge's articles:

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Xilinx SP605 DDR3 Allegro 15.7 Viewer Questions 5 70 (9/24/2011 8:40:59 PM) comp.arch.fpga I am designing a Spartan-6 pcb with DDR3 by way of Memory Control Block and with various video interfaces. Before I start with my own design, I thought I would look at other available designs, including the X... Brad

Length of Range 8 124 (11/22/2009 4:42:18 PM) comp.lang.vhdl I have this code: subtype field1 is natural range 15 downto 0; .... begin memory_data_out_update:process(clk) begin .... if(condition)then mem_do(field1)<=conv_std_logic_vector(128,16); else m... Brad

Date Time Directory Project String 4 130 (11/22/2009 4:24:17 PM) comp.lang.vhdl I am not sure that VHDL provides this. I have an FPGA with a video display and a menu module. With every revision I update a string array in the menu module that is visible on the video display. Two th... Brad

one hot machine without elsif 13 62 (2/16/2009 10:10:59 PM) comp.lang.vhdl I have a state machine done with one flag for each state. Most of the states are sequential accomplished with a default assignment: signal state : std_logic_vector(0 to 61); begin state0 then mem_out0 then ... Brad

Best Method for Count without Rollover 4 78 (5/7/2008 6:55:21 PM) comp.lang.vhdl Hi, I always run into the issue of having counters or adders where I don't want the resulting value to exceed a certain threshold. Here's an example but maybe not the best solution in terms of synthesis: sig... Brad

std_logic_vector <= my_constant 9 71 (4/28/2008 8:02:45 PM) comp.lang.vhdl Hello, For a while I have been using this verbose conversion code with numeric_std: my_std_logic_vector <= std_logic_vector(to_unsigned ( my_natural_constant,my_std_logic_vector'length)); Recently, I discove... Brad

Xilinx Tristate Registration 10 111 (3/14/2008 10:28:46 PM) comp.arch.fpga My tristate signals are not being placed in the IOBs. They are clocked signals, always all on or all off, depending on reading or writing, and the registration happens the fabric, not in the IOB. The data_out s... Brad

Simulation Constant 7 76 (2/26/2008 9:04:43 PM) comp.lang.vhdl Hello, What I would like to do is this: if( sim=true ) then constant mem_size : integer := 128; else constant mem_size : integer := 2**18; end if; But, of course, VHDL doesn't let me use "if" in the declar... Brad

ModelSim Natural arg value is negative 3 115 (2/26/2008 8:59:11 PM) comp.arch.fpga Hello Folks, Listed below is a simple NoBL SRAM model that I use to help me debug. Recently, I've been getting a ModelSim error numstd_conv_unsigned_nu Natural arg value is negative. I Googled this and found... Brad

Xilinx ISE9.2 iMPACT manual 2 231 (1/17/2008 10:16:24 PM) comp.arch.fpga Is there a complete manual for iMPACT ISE9.2 ? Can't find it. Brad Smallridge AiVision ... Brad

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Depth of logical Circuit 7 55 (6/23/2011 1:31:33 PM) comp.arch.fpga Hi all, I sythesised (with Xilinx ISE) some complex logic circuit just consisting of AND and XOR gates and I am wondering if there is any way I can identify in the post-sythese report the depth of the circuit ... sportfreund (11)

Xilinx SP605 DDR3 Allegro 15.7 Viewer Questions 5 70 (9/24/2011 8:40:59 PM) comp.arch.fpga I am designing a Spartan-6 pcb with DDR3 by way of Memory Control Block and with various video interfaces. Before I start with my own design, I thought I would look at other available designs, including the X... bradsmallridge (148)