dk4xp1809's replies:

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Creating delay chain with generics 5 41 (3/21/2012 12:46:09 PM) comp.lang.vhdl Hi I try to implement a synthesizable delay chain. Here a working example: library ieee; use ieee.std_logic_1164.all; entity delay_gate is generic ( ACTIVE_EDGE : std_logic := '1'; MA... ttobsen (14)

Green Energy Hurting Poor in Germany 44 36 (2/23/2012 5:28:43 PM) comp.dsp Green Energy = more expensive energy = poor people are left without energy. http://www.thegwpf.org/international-news/5035-green-germany-half-a-million-families-sitting-in-the-dark.html Stop being a lemming.... bulegoge (386)

Xilinx ML605 Demo Qusstion 12 44 (4/22/2011 2:30:26 AM) comp.arch.fpga I just took delivery of an ML605, and tried out the demo to make sure the board was OK. The pre-built demo is supposed to allow you to load images, and view them on the DVI or VGA output, while optionally filte... pfraser (52)

float -to - integer conversion 15 174 (3/21/2011 10:31:46 AM) comp.dsp hi sir,, whats the key logic to convert floating point number to integer. is that multiplication of floating point number and 32767 if so how does this 32767 has arrived,, waiting for u r reply,, tha... rashmi

Xilinx USB programming cable. 15 55 (2/14/2011 2:28:45 PM) comp.arch.fpga Hi, I have a 4 yr old xilinx spartan-3 starter kit which came with a parallel port JTAG programming cable. My desktop with the parallel port died recently. As desktops/laptops no longer ship with parallel port... postbox4jack (2)