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fpga.tales (1) 1 Articles, 0 Replies, 1 Points
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Since 4/14/2012 3:34:07 AM, fpga.tales has written 1 articles and participated in 0 conversations.
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Confusion in address generation for MIG generated DDR2 interface 5 176 (3/22/2010 1:46:51 PM) comp.arch.fpga Hi, I am using MIG 3.3 for generating memory interface for Micron MT4HFT3264HY-53 memory part. The user_design and example_design simulations work fine. I just need one clarification. The addresses generate... Seeker