joggingsong's articles:

Items(57) /6 Next >> Last >|

Is there a better way to implement IIR filter? 4 63 (8/7/2011 3:56:41 PM) comp.dsp Hi, all Currently, I'm working on otpimization of speech processing. Previously, my work focuses on video codec, so I have liittle experience of speech processing. In speech processing, IIR filters ... jogging

Is there a better way to optimize the implementation of IIR filter? 11 60 (8/4/2011 4:03:03 PM) comp.dsp Hi, all Recently I work on speedup of the implementation of IIR filter. Previouly my work focuses on video codec. I have litter experience on speech processing. In the processing, a IIR filter is use... jogging

antialiasing argument in function resize 1 197 (5/27/2010 2:28:29 AM) comp.soft-sys.matlab Hi, all I am using the function resize and trace it into the resize.m file. I find that there is an argument called antialiasing. I hope to use bilinear method to interpolate the image, but if antialiasin... jogging

questions about x86 2 250 (12/29/2009 7:29:25 AM) comp.arch Hi,all I have no experience in x86 assembly coding previously, but may need to optimize code on PC. So I begin to read the manuals doawloaded from Intel's website. In the diagram of intel core microarchit... jogging

shift direction using correlation 2 139 (12/23/2009 11:18:08 AM) comp.soft-sys.matlab In case 1, signal2 should be right shift by 2 to be same as signal1. In case 2, signal2 should be left shift by 2 to be same as signal1. For the ease of programming, I expect dshift can have a sign to indica... jogging

shift direction using correlation 2 225 (12/23/2009 11:16:48 AM) comp.dsp Hi, I am trying to determine the signal shift by correlation method. The following is the matlab code: %case 1 Signal1 = zeros(1,32); Signal1(3:13) = 8; Signal2 = zeros(1,32); Signal2(1:11) = 8; Id... jogging

question about nonaligned memory access 50 103 (9/16/2009 3:51:12 PM) comp.arch Hi, Nowadays I am working on optimization on DSP. I encounter nonaligned memory access. I have several questions about it. First, why some processors don't support nonaligned memory access? To simplify th... jogging

cache miss on x86 6 237 (8/14/2009 11:55:56 AM) comp.arch Hi, Recently I learned that cache miss can result in several hundreds cycles. I am a little confused. Most of my work focuses on DSP. If this happen on DSP, the penalty is not costly, about several tens ... jogging

the performance of x86 processor and DSP 38 48 (8/6/2009 3:35:40 PM) comp.dsp Hi, I am a engineer and have done much work on DSPs. Compared to x86 processor, DSP has low power consumption and is a SOC, so it is a ideal choice for portable equipments. Before I have worked on a board ... jogging

memory access performance on C64x+ 0 46 (5/12/2009 6:50:34 AM) comp.dsp Hi, I am reading the spru862b of TMS320C64x+ DSP Cache User's Guide.L1D miss penalty is 12.5 cycles. I am a little confused why the penalty is so large though L2 operates in the same frequency of L1D. For ... joggingsong

joggingsong's replies:

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Why not the two cores in DaVinci are merged into one core? 13 51 (12/10/2007 9:25:01 AM) comp.dsp Hi,all We know there are one ARM core and C64x core in DaVinci from TI. The ARM core is for OS and C64x is for DSP. Is it possible to merge two cores into one? This idea is crazy? It makes me think of XScal... joggingsong (102)

H.264 or MPEG-4 for Surveillance? 5 53 (12/19/2007 2:53:01 PM) comp.dsp Hello, Suppose you have a surveillance project on which two 4-CIF NTSC streams (704 x 480) @ 15 fps have to be encoded for network streaming and for storage, and that the network bandwidth is up to 2 Mbps. Al... jaime.aranguren (90)

Corner detection on digital signal processor 6 50 (12/21/2007 11:46:39 AM) comp.dsp Hello, I need to develop an algorithm to create a coarse optical flow field from a video signal for motion analysis in real time on a TI DSP c6400. This requires tracking low level features (corners). There are... peterbone1 (8)

DSP architetcure diagrams - appropriate levels for features 7 49 (1/7/2008 12:51:50 PM) comp.dsp Diagrams that overview DSP architectures seem to me sometimes to mix low-level features with high-level ones. For instance TI's high-level block diagram for their Da Vinci processor: eg at http://focus.ti.com... chris.bore (194)

I think prefetch instuction should be supported in C64x+ 12 54 (1/4/2009 1:27:01 AM) comp.dsp Hi, all In DSP, it can generate cache miss if you access memory sequentially. DMA can transfer data from external memory to internal memory.But sometimes the access pattern is not easy to use DMA. I think i... joggingsong (102)

the pipeline of C64x+ 4 44 (3/23/2009 7:38:00 AM) comp.dsp Hi,all I am a DSP engineer for a few years. But till recently I have a chance of programming on C64x+ from TI. One difference of C64x+ from other DSPs I have used is the pipeline. The execution stage of pipe... joggingsong (102)

the performance of x86 processor and DSP 38 48 (8/6/2009 3:35:40 PM) comp.dsp Hi, I am a engineer and have done much work on DSPs. Compared to x86 processor, DSP has low power consumption and is a SOC, so it is a ideal choice for portable equipments. Before I have worked on a board ... joggingsong (102)

Instruction Cache Optimisations 5 47 (11/14/2007 2:58:15 PM) comp.dsp Hi, in the recent days I was reading an article describing how to optimise instruction cache behavior by modifying the placement of functions in memory. The article can be found under: http://www.dspdesignli... plfriko (499)

different data width? 3 58 (11/20/2007 3:51:16 AM) comp.dsp Hi, all In the BDTI's pocket guide, there is a column, Data Width, which divides DSPs into different groups. For TMS320C64x+, the data width is 8/16 bits. For blackfin, the data width is 16 bits. Registers i... joggingsong (102)

when are these dsp cores introduced to market? 6 66 (11/27/2007 1:31:50 PM) comp.dsp Hi, I hope to find when the dsp cores from TI, ADI, and Freescale are introduced to market? I searched the internet, but haven't found the useful information. For TI, it seems that it first introduced C62x ... joggingsong (102)