jprovidenza's articles:

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FPGA + HDMI 1080P 3 57 (7/20/2012 2:08:50 AM) comp.arch.fpga I'm looking for a FPGA board that can support HDMI/DVI 1080P in/out. I'd like to avoid building my own, I'm probably looking at a volume of 100 units. Any thoughts/suggestions? Thanks! John P ... johnp

Verilog, VHDL, sync and async resets 1 98 (8/10/2011 10:53:16 PM) comp.arch.fpga We need to code some modules in both VHDL and Verilog and would like to use a parameter/generic to control inferring sync or async resets. Is there a clean way to code this that is similar in both VHDL and Ver... johnp

J1 forth processor in FPGA - TCP/IP implementation? 2 62 (5/25/2011 2:38:57 PM) comp.lang.forth Someone else started a thread recently on the J1 processor. It's an interesting looking project, but I don't really see TCP/IP implemented. It has some support for IP and UDP, but the actual TCP protocol seem... johnp

OMAP2 docs? 2 435 (12/15/2009 5:39:45 PM) comp.dsp Does anyone have a copy of the Texas Instruments OMAP2 Tech Ref Manual they could send me? I'm not able to find it on the web. Thanks! John P. ... johnp

EZUSB-FX2 board bring-up - dead clock - solution 0 55 (1/13/2009 11:26:51 PM) comp.arch.embedded I just finished debugging a FX2 board design and thought I would proactively post the solution to a problem that may bite other people. The FX2 has a pin called "reserved". The board designer left it floating ... jprovidenza

jprovidenza's replies:

Items(8) /1

FPGA + HDMI 1080P 3 57 (7/20/2012 2:08:50 AM) comp.arch.fpga I'm looking for a FPGA board that can support HDMI/DVI 1080P in/out. I'd like to avoid building my own, I'm probably looking at a volume of 100 units. Any thoughts/suggestions? Thanks! John P ... jprovidenza (15)

VHDL syntheses timestamp 7 49 (4/21/2012 8:52:22 PM) comp.arch.fpga Hello all, I want to implement a "build" timestamp into some FPGA Designs (like the C __DATE__ makro). Optimal would be someting like the 32Bit unix timestamp. Does anybody know if there is some method to gen... arne6338 (4)

Data Transfer from PC to FPGA through USB 7 127 (4/10/2012 1:10:33 PM) comp.arch.fpga Hallo guys, I'm pretty new to hardware programming. I'm currently working on a project and I have to create a communication channel between my PC and FPGA (Xilinx Virtex 5 model) through a USB port. At the en... mtnyenty (1)

gigabit ethernet problem 16 54 (9/22/2011 7:21:23 PM) comp.arch.fpga Hi, I am using xilinx spartan3 xc3s4000 in my design. It is interfaced with 2 national Gigabit PHYs. So i receive a packet from phy A and transmit it to PHY B and vice versa. Now the problem i am facing is that... a12345731 (38)

DVI-decoder clock question 3 48 (7/29/2011 1:59:46 PM) comp.arch.fpga Let say I have two DVI streams - generated by two encoders, those have different video contents but same pixel clock The two tmds streams travel thru cables then - are decoded by two decoders - then fed into a... ccon67 (38)

Random Reset calls 1 51 (6/1/2011 9:40:51 AM) comp.arch.fpga Hi Folks, Need something interesting in random reset: I am having a testbench in verilog which needs to hit the state machines states with reset. Basic Format of testbench: ##############3 initial begin ----... rsgupta.gupta (3)

J1 forth processor in FPGA - TCP/IP implementation? 2 62 (5/25/2011 2:38:57 PM) comp.lang.forth Someone else started a thread recently on the J1 processor. It's an interesting looking project, but I don't really see TCP/IP implemented. It has some support for IP and UDP, but the actual TCP protocol seem... jprovidenza (15)

External clock in cypress EZ-USB FX2 4 28 (6/30/2009 11:55:51 AM) comp.arch.embedded hello, I am working on a cypress chip. I want the communication between endpoints and host to work on external clock. Is it possible for chip to work on external clock without being in Slave FIFO or GPIF mode? ... sanika.sani (6)