kaushik.priyanka's articles:

Items(9) /1

Simulation of multipath 7 28 (6/18/2009 1:45:43 PM) comp.dsp Hi all, I am interested in knowing how to simulate a multipath channel. ... priya

regarding zero padding and Cyclic prefix 7 31 (6/17/2009 2:41:48 PM) comp.dsp Hi all, I have just started reading about the OFDM systems .I have read in some paper that zero padding is advantageous over Cyclic prefix approach. In most of the systems i have found Cyclic prefix there not z... priya

ASCII File 3 83 (9/10/2007 5:58:40 AM) comp.lang.vhdl hi frens i am writing a VHDL test bench.i want to read a file in ASCII format. Cann any one tell me if thr is any package available. ... priya

pst translate simulation 1 52 (9/10/2007 5:45:02 AM) comp.lang.vhdl Hello frens i had written some module in VHDL. I had verified the functionality of the module (Functional simulation- Modelsim). but after POST translation when i m simulating i m getting garbage value. wat cud... priya

need help #7 1 86 (8/7/2007 9:07:01 AM) comp.lang.vhdl hallo frens i had encountered an error during synthesis i m using Xilinx ISE7.1 can u make out wat FCT means failed to translate terminal to FCT $n0584= If $n0354 Then $n1362 If $n0355 Then $n1274 If $n0356 Th... priya

Divison Operation 2 61 (12/7/2006 11:09:01 AM) comp.lang.vhdl hi all i have to implement the following expression in vhdl ratio=y1/y2 i tried to use mod operation but it has a constraint that the operand n operator(one of them) must be constant or of power of 2. i tried ... priya

How to find the ABS of std_logic_vector 3 376 (11/21/2006 11:48:28 AM) comp.lang.vhdl hi ABS function which is specified for integer type in VHDL for slv data type how to find the absolute value reply back soon ... priya

signed multiplication 2 51 (11/16/2006 3:52:30 AM) comp.lang.vhdl hi all Y<=Y+(A*B-C*D); where y,A,B,C,D are STD_LOGIC_VECTOR form. here A,B,C,D are all variables since by default STD_LOGIC_VECTOR is Unsigned . so the result which i m getting is not what is required. since i... priya

MODULUS operator 3 71 (11/15/2006 7:39:50 AM) comp.lang.vhdl hi all i m using integer data type in VHDL .i have to perform modulo operation. but the problem i m facing is that the operand must be a constant like A<= (A+1) MOD X where X is not a constant. during synthesis... priya

kaushik.priyanka's replies:

Items(2) /1

Simulation of multipath 7 28 (6/18/2009 1:45:43 PM) comp.dsp Hi all, I am interested in knowing how to simulate a multipath channel. ... kaushik.priyanka (13)

regarding zero padding and Cyclic prefix 7 31 (6/17/2009 2:41:48 PM) comp.dsp Hi all, I have just started reading about the OFDM systems .I have read in some paper that zero padding is advantageous over Cyclic prefix approach. In most of the systems i have found Cyclic prefix there not z... kaushik.priyanka (13)