Since 4/2/2012 5:22:53 AM, ksulimma has written 5 articles and participated in 21 conversations. ksulimma signature: ksulimma
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Desperately looking for XC5VFX30T-3FFG665339 (4/13/2011 3:03:22 PM) comp.arch.fpga Hi, for our new product we are using the chips in the subject of this post. The last time we ordered they had 4 weeks leadtime. Therefore we did not take any special precautions to procure chips. Now the next... Kolja
1250gbps input on virtex-56116 (5/22/2008 1:13:06 PM) comp.arch.fpga Hi, we need to input a continous stream of 32 LVDS data bits at 1.25gbps per pin into a Virtex-5. There is a clock provided for each byte (source synchronous). There was a news item by Xilinx that says this i... Kolja
clock distribution accross boards1340 (3/3/2008 4:27:15 PM) comp.arch.fpga Hi, maybe you folks can help me with a design decision: I need to distribute a clock to up to ten identical boards. The boards are all plugged into a backplane in a single row. In addition to the backplane t... Kolja
Fixedpoint Multiply/Accumulate in DSP484187 (1/25/2008 1:47:36 PM) comp.arch.fpga Hi, am a little confused as far as the capabilities of the DSP48 go. I would like to implement a 18x35 MACC in (hopefully) only two DSP48. The 18 bit coefficient is a 0.18 fixed point number. I.e. what I reall... comp
Virtex 4 FX Sonet Alignment6100 (2/28/2007 2:47:10 PM) comp.arch.fpga Is there anybody in this group who has experience with V4FX MGT Sonet Alignment? The documentation is rather short on details. The interaction of the two alignment stages is not clear to me at all. What we see... comp
VHDL horror in Xcell 76780 (7/27/2011 9:53:44 AM) comp.arch.fpga There is an utterly horrible VHDL howler on page of 45 of the latest Xcell Journal. Two example codes for a register with reset are given: signal Q: std_logic:=‘1’; .... async: process (CLK,RST) begin if (R... robert.ingham2755(75)
extracting D from 1 / D*D1339 (8/17/2011 11:11:10 AM) comp.arch.fpga Hi Folks, Incredibly busy summer here, so before burning my brain cells, Googling or -worst- digging in my very dusty math courses, I submit this question to the DSP experts who usually float around, hoping s... do_not_spam(8)
PCI Express development board1756 (11/4/2011 11:15:15 AM) comp.arch.fpga Hi, I'm looking for an FPGA-based PCI Express development board which is capable of transmitting data at about 1.4 GByte/sec to the host computer (PCIe Gen1 x8 or Gen2 x4/x8). Further considerations: 1. inclu... zsolt.garamvolgyi(7)
LUT6 FPGAs and Carry Logic1542 (2/14/2012 11:13:38 PM) comp.arch.fpga Hallo. Some questions about Xilinx LUT6 FPGAs (my WebPack Toolchain is a little outdated, and the newer LUT6-FPGAs don't seem to show up correctly in fpga_editor). * Is there really no carry-bypass option in... jansaccount(1)
FPGA Area648 (3/6/2012 1:43:14 PM) comp.arch.fpga Hi all, I have question on measuring FPGA area. Measuring area cost of the FPGA implementation is tricky because there are several different area types LUT, FF, BRAM, DSP. Is there way look at a uniform cost m... shakith.fernando(5)
Generate a pulse with a definite width855 (7/2/2012 9:26:51 AM) comp.arch.fpga hi
is it a good practice to generate a pulse strobe in Verilog with this code?
or do i need to write a fsm for such applications?
BoardConfigReceivedStrobe is set elsewhere in the process. for resetting
thi... nba_baheri1(11)