maxascent's articles:

Items(11) /2 Next >> Last >|

EDK problems 2 72 (5/28/2012 8:20:40 PM) comp.arch.fpga Does anyone have experience of using the Altera and Xilinx embedded software? I have been using EDK but I am getting very frustrated with it. It seems that every new release includes a generous helping of bug... maxascent

VHDL connection problem 3 57 (10/5/2011 1:35:57 PM) comp.arch.fpga I have a memory that output a 64-bit slv. I have another module that has a record type with a data 64-bit slv input. I want to connect the two together. If I do this I get x. If I disconnect them the mem output... maxascent

Testbench #2 4 66 (10/4/2011 3:16:40 PM) comp.arch.fpga I would like to write a testbench in VHDL using constrained random values and transactions. Are there any free packages that people know about that do this sort of thing? TIA ----------------------... maxascent

VHDL problem 4 60 (9/30/2011 3:24:22 PM) comp.arch.fpga I want to do something like this signal slv : std_logic_vector(7 downto 0); signal sl : std_logic; signal res : std_logic; res <= slv = x"01" and sl = '1'; But I get an error. I guess its something to do wi... maxascent

VHDL Basic Question 11 55 (8/20/2011 2:47:16 PM) comp.arch.fpga I am new to VHDL and need some advice on connecting a vector array on an entity using a port map.I have an array of std_logic_vectors(63 downto 0) as a port. There are 3 of these in the array. How do I connect ... maxascent

Modelsim #3 5 55 (5/18/2011 2:46:26 PM) comp.arch.fpga Does anyone know if its possible to change the waveform signals so that they are in hex instead of binary. I dont want to do it manually but just have it come up in hex when the design is loaded. Thanks Jon ... maxascent

Virtex 5 PCIe Debug 0 48 (4/2/2011 10:38:59 AM) comp.arch.fpga I am trying to debug a Virtex 5 PCI Express core. When I insert it into a PC it is not detecting it. I have chipscope connected to the LTSSM state machine signals and it seems to be stuck in state 2. Is there a... maxascent

Virtex 5 GTP Simulation 2 373 (10/29/2010 3:08:58 PM) comp.arch.fpga I have a Virtex 5 design that uses a GTP. I have a simple simulation that justs transmits some data and looks at the received data. The simulation works fine and I see the correct received data. The trouble i... maxascent

data2mem 0 231 (4/26/2010 2:02:01 PM) comp.arch.fpga I am using data2mem to generate some .mem simulation files. My address for memory starts at 0x86000000 and if I dump the elf file I can see that. However when I run data2mem the .mem file starts at address 0x... maxascent

Microblaze Reset 1 536 (4/11/2010 3:57:22 PM) comp.arch.fpga Is it possible to define an internal reset for a microblaze system. Idealy I would like it to come from the DCM locked signal. Do I need to define it in the XBD file or is that just for external ports? Tha... maxascent

maxascent's replies:

Items(29) /3 Next >> Last >|

Bitstream compression #2 16 67 (7/28/2011 11:47:44 PM) comp.arch.fpga Hey all-- So my experience with the native bitstream compression algorithms provided by the FPGA vendors has been that they don't actually achieve all that much compression. This makes sense given that the ... rgaddi (162)

Newbie PCB 8 44 (8/8/2011 11:52:10 AM) comp.arch.fpga Hi there! I need some advice. I want to make a circuit to drive a VGA monitor. I've done it with the FPGA trainer boards with Xilinx chips, but now I want to design a custom board that host only the necessary ... linobi (1)

VHDL Basic Question 11 55 (8/20/2011 2:47:16 PM) comp.arch.fpga I am new to VHDL and need some advice on connecting a vector array on an entity using a port map.I have an array of std_logic_vectors(63 downto 0) as a port. There are 3 of these in the array. How do I connect ... maxascent (59)

VHDL problem 4 60 (9/30/2011 3:24:22 PM) comp.arch.fpga I want to do something like this signal slv : std_logic_vector(7 downto 0); signal sl : std_logic; signal res : std_logic; res <= slv = x"01" and sl = '1'; But I get an error. I guess its something to do wi... maxascent (59)

most stable version of ISE ? 3 72 (10/3/2011 10:24:42 AM) comp.arch.fpga I've seen lots of messages a while ago about how ISE is going downhill... Which version of ISE would people recommend for fairly simple VHDL projects using Spartan-3 and Spartan-6? I'm currently developing wi... mike4785 (311)

VHDL connection problem 3 57 (10/5/2011 1:35:57 PM) comp.arch.fpga I have a memory that output a 64-bit slv. I have another module that has a record type with a data 64-bit slv input. I want to connect the two together. If I do this I get x. If I disconnect them the mem output... maxascent (59)

Xilinx PCI Express - Am I starting too low? 4 73 (11/15/2011 5:42:33 PM) comp.arch.fpga Hello, I have used the Xilinx LogiCore Integrated Block for PCI Expres several times in the past. On those occasions I have hacked into the autogenerated example design to bring a standard parallel interface u... padudle (12)

=?ISO-8859-1?Q?Post=2Dsynth=E8se_simulation?= 5 68 (1/29/2012 2:59:22 PM) comp.arch.fpga Hello, I want to run a post-synthesis simulation. I don't find where to choose the sources (Netlist post-synthesis) to launch the needed simulation from ISE 13.3. Does someone know how to do it ? I need some ... molka.benromdhane (2)

Very poor Xilinx experience 10 59 (4/3/2012 9:43:05 PM) comp.arch.fpga I'm hoping someone at Xilinx reads this, because I can't find any other way to get through to anyone to help me. Short version: I've bought an SP605 board, it looks as though it's broken - there's no video out... google115 (67)

Data transfers between MicroBlaze and VHDL 11 159 (6/19/2012 7:26:35 PM) comp.arch.fpga I am using EDK 14.1 and a Spartan-6 FPGA (potentially changing FPGAs in the future to the Artix 7 or Kintex 7). I am trying to figure out a way that I could output the data from the MicroBlaze to a VHDL mod... robert.higginbotham0 (4)