michaelrbodnar's articles:

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Get size of remote file using ftpLib (VxWorks 6.5) 1 45 (2/13/2012 6:40:58 PM) comp.os.vxworks Is this possible? The API suggests that I can send arbitrary commands, but I am having difficulty obtaining the response (e.g., of "LS" or "SIZE" or "DIR", etc.). ... MBodnar

michaelrbodnar's replies:

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Problems with Xilinx SDK and LwIP 5 1191 (3/3/2011 12:01:12 AM) comp.arch.fpga Alright, so I'm trying to compile the example projects from xapp1026, following the instructions included in xapp1026.pdf: www.xilinx.com/support/documentation/application.../xapp1026.pdf I'm using the Xil... DaMunky89

Best FPGA for algorithmic acceleration 9 50 (4/9/2012 5:13:41 AM) comp.arch.fpga Hello, I'm looking at different options to use FPGAs as coprocessors for algorithmic acceleration. Between the Xilinx Virtex 6 (LXT or SXT), or the Altera Stratix IV (360, 530 or 820), what would be my best op... jfix71 (2)

Ethernet Intialization in vxworks 6.7 2 140 (5/3/2012 8:47:21 AM) comp.os.vxworks hai all I am using ipcom_drv_eth_init and followed by ifconfig for initializing the Ethernet Channels but after the compilation i am getting warning implicit declration of ipcom_drv_eth_init and ifconfig Pls... raghumtech (6)

programatically find own IP Address and if dhcp is enabled 1 44 (7/25/2012 3:45:49 PM) comp.os.vxworks I am currently porting a windows app to vxWorks 6.9 and need to access the IP address of the vxWorks target and also find out if this has been statically assigned or if it was assigned by dhcp. The target b... david8109 (1)

VHDL problem 4 54 (9/30/2011 3:24:22 PM) comp.arch.fpga I want to do something like this signal slv : std_logic_vector(7 downto 0); signal sl : std_logic; signal res : std_logic; res <= slv = x"01" and sl = '1'; But I get an error. I guess its something to do wi... maxascent (59)

Can a vhdl function return a range? 5 60 (12/16/2011 6:53:47 PM) comp.lang.vhdl I'd like to use a function to compute the 'X downto Y' range of a vector. Is there a clean way of doing this? -- something like this would be nice: function get_slice(n : natural) return range is begin retu... mksutherland5 (2)

Active-HDL/Xilinx Core FIFO Gen Sim Problem 4 38 (1/30/2012 5:32:29 PM) comp.lang.vhdl Hi there, I'm using Xilinx 10.1(nt) K.31, and Aldec Active-HDL 8.1 (student). I used Aldec's design flow tools to implement a Coregen FIFO, and am using a recent, manufacturer-compiled version of XilinxCoreLib.... roleohibachi (3)

Get size of remote file using ftpLib (VxWorks 6.5) 1 45 (2/13/2012 6:40:58 PM) comp.os.vxworks Is this possible? The API suggests that I can send arbitrary commands, but I am having difficulty obtaining the response (e.g., of "LS" or "SIZE" or "DIR", etc.). ... michaelrbodnar (11)

numeric_std package 6 56 (2/17/2012 12:03:51 AM) comp.lang.vhdl Hi all, I have recently started using the package IEEE.numeric_std to deal with unsigned numbers (as opposed to IEEE.std_logic_arith). I would like to check if an unsigned number is a zero by logical OR operati... ramya.murali.d (3)