mottoblatto's articles:

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Initializing Micron DDR2 Memory 4 103 (12/12/2007 4:03:12 AM) comp.arch.fpga Does anyone know a way to initialize DDR2 memory models from Micron with data....easily? I have 16 DDR2 SDRAM models connected in a 2 Gigabyte SODIMM configuration. The problem I am facing is that our EDK sys... motty

How to use an internal signal in a testbench... 3 176 (10/27/2007 5:32:18 AM) comp.arch.fpga I am simulating an EDK system and want to use some internal signals at the testbench level (without routing them up to external ports). I thought that you could simply do this by assigning signals using hierac... motty

MPMC2 NPI Help! 9 42 (10/24/2007 9:33:06 PM) comp.arch.fpga I am using the MPMC2 to implement a PLB and NPI port config. The PLB port works as expected. However, I am simulating my design and the NPI isn't working as I expect. I have created a small NPI interface tha... motty

Xilinx FIFO Flag Question 0 132 (10/16/2007 1:59:55 AM) comp.arch.fpga I generated a 32-bit by 1024 entry FIFO using the FIFO Generator. The FIFO is an independently-clocked BRAM that has a 39 MHz clock on the write side and a 100 MHz clock on the read side. I am writing one 32-... motty

Timing Constraint Question 1 119 (10/9/2007 8:41:44 PM) comp.arch.fpga I am working with an EDK design that utilizes an MPMC2 core. There are several clocks associated with this core. All of the clocks are created using DCM's and inverters. I am failing timing b/c cross- clock ... motty

PowerPC Simulation 2 111 (9/27/2007 7:46:56 PM) comp.arch.fpga I am simulating the PowerPC and can't find the damn program counter. I have looked in the reference manuals that come with the EDK but can't find any helpful info!! Anyone know where to point me? I am using M... motty

Beyond Newbie Question 8 59 (9/13/2007 2:45:10 PM) comp.lang.vhdl I will not even consider myself a newbie in VHDL. I am trying to hack someone else's code to do what I need it to do...which is trivial. I am using Xilinx tools by the way. I have a signal coming into a modu... mottoblatto

DDR Simulation via MIG 2 110 (9/6/2007 10:54:09 PM) comp.arch.fpga I am looking into a MIG-generated DDR SDRAM interface and am having trouble with the simulation. I can see the interface go through the intialization sequence, but when it gets to the first dummy read to cal t... motty

FIFO Full logix - V4 2 98 (7/23/2007 1:33:37 AM) comp.arch.fpga I am working with a dual port RAM FIFO module that has a 32-bit write port and an 8-bit read port using asynchronous clocks. The full and empty flags use static thresholds...meaning I didn't choose the program... motty

DIFF_TERM Question 3 132 (7/3/2007 3:21:10 PM) comp.arch.fpga For a Xilinx V4, there is an IBUFDS_DIFF buffer that you can use in the I/O pad. However, it appears that there is no differential termination resistor available for this setup. In XAPP861, it shows the buffe... motty