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Altera Flex10K support ? 5 37 (8/17/2011 7:07:51 PM) comp.arch.fpga Hi I have found old parts lying around in the lab and I could put them to good use. Alas, they are not supported by Quartus any more. Do you know which version of the tool I should get (and where I could get ... Nicolas

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Which to learn: Verilog vs. VHDL? 48 114 (4/14/2008 1:18:15 PM) comp.arch.fpga Howdy - I'm just beginning with FPGAs. I am using a Spartan 3E Starter Kit with Xilinx ISE. I am an electrical engineer by training and did some verilog in my collegiate days - but that was quite some time ago ... nleahcim (113)

Button clock 5 28 (1/18/2013 8:32:08 PM) comp.arch.fpga Hi to everyone! This is my first message here so first of all thanks to everyone to let me post here! I have a homework, it consists on writing a processor and make it work in a Spartan 3. I did the fir... tupadre

Altera Flex10K support ? 5 37 (8/17/2011 7:07:51 PM) comp.arch.fpga Hi I have found old parts lying around in the lab and I could put them to good use. Alas, they are not supported by Quartus any more. Do you know which version of the tool I should get (and where I could get ... nicolas.matringe (18)

FPGA communication with a PC (Windows) 33 124 (3/27/2012 11:10:18 AM) comp.arch.fpga Hello all, My team needs to design our own piece of testing equipment for our project. I'll spare you the gory details, and just say that we will need to collect data at some 20 Mbyte/sec (possibly continuousl... bill.valores (7)

vhdl IRC 4 20 (5/12/2012 10:51:29 AM) comp.lang.vhdl Hi I'm trying to figure out how to work with vhdl (Xilinx - Digilent Basys 2 (spartan 3e starter board)) to ask some "noob" questions about the language ... maregt0 (1)

Xilinx ISE Multiple Drivers Error 15 284 (5/17/2012 6:15:34 AM) comp.arch.fpga Hi folks, I seem to have convinced ISE to output incorrect multiple-driver error messages. I've reduced the example to the following: -- test.vhd library ieee; use ieee.std_logic_1164.all; entity Test is por... chead (39)

Check all bits set 10 27 (6/22/2012 4:55:40 PM) comp.lang.vhdl library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; signal WRaddr : unsigned(11 downto 0); if rising_edge(CLK) then if WRaddr/="111111111111" then WRaddr <= WRaddr +1; ... aleksaZR (112)

clk event at firs simulation cycle 3 20 (9/4/2012 12:03:28 PM) comp.lang.vhdl signal w_clk : std_logic := '1' ; The clock condition does not pass on the first sim cycle in Modelsim. Why? read_stimuli : process(w_clk) if(w_clk'event and w_clk='1') then ... do9853 (64)

Xilinx XC3S400 reproducibility madness 7 44 (11/5/2012 10:53:53 AM) comp.arch.fpga Hello all I am facing a strange problem: I am not able to generate a properly working= bitstream from an original set of files that worked perfectly well just a = few days ago. I mean, the FPGA gets program... nmatringe (6)

VHDL expert puzzle 72 36 (11/25/2012 7:11:43 PM) comp.arch.fpga In the following link, a design is presented that alledgedly has a flaw. The claim is that this is a simple case and that any experienced designer will see the flaw immediately. (I don't.) http://www.pr... jan1052 (53)