oktem User Profile

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timing constraint syntax/fpga editor info 2 224 (2/24/2010 7:48:32 AM) comp.arch.fpga What is the syntax of this below constraint? I am using xilinx 11.4, spartan 6, and VHDL I have a signal say "a" that goes to 2 different "obufds". The delay between this "a" signal to the pins/pads are ... Serkan
free waveform drawing tool 10 788 (2/5/2010 9:28:06 AM) comp.lang.verilog Any suggestions for a free waveform drawing tool? inkscape or word alike tools take too much time for edition. some free tools does not let more than 10 clock cycles some free tools does not let more... Serkan
IMPACT-Xilinx Platform Cable USB II 6 61 (9/8/2009 12:18:20 PM) comp.arch.fpga I have a custom board that uses usb and has 2 fpgas (spartan3 200 - spartan 3 4000) I am using Xilinx platform cable USB II to program the fpga I am using windows xp pro I am using Xilinx 9.1.03i When I press... Serkan
pre-initialized dpram functional simulation 0 115 (6/25/2009 8:50:16 PM) comp.arch.fpga I am using Xilinx ISE 9.1.i and Modelsim XE 6.2C I am generating a dpram_32k using Core Generator. All I can see is 0s (zero) at the output. How can I see pre-entered initial values in the functional simulatio... Serkan
pre-initialized dpram functional simulation 9 62 (6/25/2009 8:47:30 PM) comp.lang.vhdl I am using Xilinx ISE 9.1.i and Modelsim XE 6.2C I am generating a dpram_32k using Core Generator. All I can see is 0s (zero) at the output. How can I see pre-entered initial values in the functional ... Serkan
set dont touch in Xilinx Xst 2 270 (6/19/2009 2:49:15 PM) comp.arch.fpga Is there a "set_dont_touch" equaivalent version of Xilinx Xst attribute. Or is it only in synopsys?. ... Serkan
hard macro basic clock reset question 1 111 (4/27/2009 2:56:17 PM) comp.arch.fpga I'm making a hardmacro usinx Xilinx 9.1.03i Fpga Editor. My implementation will be on Spartan 3 200. I am trying to connect resets of the Slices and make only one reset input for my macro in the top module of ... oktem
integer to binary conversion with fixed output width 6 20 (3/6/2009 6:49:11 AM) comp.lang.tcl Im having problem with integer to binary conversion. Is there a tcl function that I can determine the width of the output. if I convert 3 to binary can I get an output of exactly 4 bits like this (0011) I do ... oktem
writing current date to a 32 bit register 8 79 (3/4/2009 11:39:27 AM) comp.lang.vhdl I want to automatically put the current date (year,month,day maybe hour) in a 32 bit register during the synthesis stage. I am using Modelsim as a simulator and Xilinx Xst as a synthesis tool. My target fpga is... oktem