Since 4/2/2012 5:32:25 AM, s_krustev has written 1 articles and participated in 0 conversations. s_krustev signature: s_krustev
var keyword in SystemVerilog41342 (1/28/2010 4:17:33 PM) comp.lang.verilog A simple question about the keyword ' var ' in SystemVerilog. I'm not
sure I understand its significance reading the standard. Esspecially
when it is used in the port lists.
How this relates to the synthesys... siso