ttobsen's articles:

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Creating delay chain with generics 5 42 (3/21/2012 12:46:09 PM) comp.lang.vhdl Hi I try to implement a synthesizable delay chain. Here a working example: library ieee; use ieee.std_logic_1164.all; entity delay_gate is generic ( ACTIVE_EDGE : std_logic := '1'; MA... Tobias

Detecting bit transistion in std_logic_vector 14 31 (2/15/2012 3:56:02 PM) comp.lang.vhdl Hi everybody I have a 32 bit std_logic_vector, for example something like this: 00010101111111111101010000000000 Now I want to find the place where the 1's start to be constant for at least five times and w... Tobias

EDK - program behavior 3 42 (3/29/2011 4:13:12 PM) comp.arch.fpga Hi Last time I asked something about max array size. Now I have another problem and I think it has also to do with the memory. When I have a bigger program, sometimes it run how I want. But if I commented s... Tobias

contourplot in xy plane of Graphics3D 2 26 (9/2/2009 8:02:24 AM) comp.soft-sys.math.mathematica Hi All I need to show a contourplot in the xy-plane of an Graphics3D. I tried with inset, but it doesn't work because there's an error message: "Inset is not a Graphics3D primitive or directive." Than... Tobias

problem with integrating an interpolated list 3 45 (8/29/2009 10:32:59 AM) comp.soft-sys.math.mathematica Hi I've an problem with integrating an interpolated list. I use Mathematica 7 and I'm a pretty newbie. I generate a list of lists like this List2D = {{0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 5,... Tobias

ttobsen's replies:

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Detecting bit transistion in std_logic_vector 14 31 (2/15/2012 3:56:02 PM) comp.lang.vhdl Hi everybody I have a 32 bit std_logic_vector, for example something like this: 00010101111111111101010000000000 Now I want to find the place where the 1's start to be constant for at least five times and w... ttobsen (14)

Creating delay chain with generics 5 42 (3/21/2012 12:46:09 PM) comp.lang.vhdl Hi I try to implement a synthesizable delay chain. Here a working example: library ieee; use ieee.std_logic_1164.all; entity delay_gate is generic ( ACTIVE_EDGE : std_logic := '1'; MA... ttobsen (14)