water9580's articles:

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TCP/IP offload in hardware 1 226 (12/7/2009 9:18:32 AM) comp.arch.fpga Anyone have TCP/IP offload (TOE) core in FPGA or design experience? plz mail: arcdoos@yahoo.com ... water

is it a bug?(Xilinx Xapp859 reference design: DDR2 SDRAM controller) 3 109 (12/5/2008 10:37:46 AM) comp.arch.fpga The 345th line of dma_ddr2_if.v file is: xfer_cnt <= xfer_cnt - 3'b10; why to substract 2,not 1? eg: read 64bytes data from SDRAM.it needs four times for 16bytes/xfer. But,it only reads two times beca... water9580

it doesn't work if increase a little traffic for DMA read. 2 77 (5/23/2008 1:30:57 PM) comp.arch.fpga The unidirection DMA read only or write only of my PCIE NIC controller V5-based works fine . However,if DMA read(from host--->ethernet port) is progress ,additional i send ping packet continuing from Host or... water9580

I use a ftp tool test my V5-based PCIE ethernet NIC controller. 0 95 (4/29/2008 10:45:58 PM) comp.arch.fpga 1>uni-upload or uni-download,it works well.occasionally ,the NMI error is trigered if the PH credit is changed from (4)finite to (0)infinite . why can the PH credit become infinite? it is normal? 2>if up... water9580

frame value too large by ifconfig!!!! 4 25 (2/24/2008 2:49:10 AM) comp.os.linux.networking my NIC doesn't work .My os is RHEL5.1/32bit/dual core intel cpu. the ifconfig output: eth2 Link encap:Ethernet HWaddr 00:55:7B:B5:7D:F7 inet addr:192.168.1.22 Bcast:192.168.1.255 Mask:255.255.255.0 inet6 addr:... water9580

Xilinx PCI-express coregen 1 154 (11/4/2007 3:21:31 PM) comp.arch.fpga There are some MAXDELAY=1ns constrain for TX signals inside PCIE coregen. eg: (* MAXDELAY="1.0" *) wire [1:0] tile0_txcharisk0_r; (* MAXDELAY="1.0" *) wire tile0_txdetectrx0_r; (*... water9580

Xilinx PCI-Express Endpoint Block IP 2 143 (11/4/2007 2:03:03 PM) comp.arch.fpga There is only 8 bit interface wrapper(pcie_gt_wrapper.v) from Xilinx PCI-Express Endpoint Block IP. it means that it needs 250MHz clk.In general,it is impossible to achieve 250Mhz clk with large design.So,we ne... water9580

how do Xilinx PCSPMA IP core detect presence of optical input? 0 102 (7/21/2007 12:28:37 PM) comp.arch.fpga I use Xilinx PCSPMA GTP IP core to connect SFP interface. But how to connect the signal_detect signal of PCSPMA GTP core to indicate presence of optical input? ... water9580

ML555 SFP module 3 218 (7/8/2007 4:49:56 AM) comp.arch.fpga I use Xilinx PCSPMA GTP IP core to connect ML555 SFP interface. But how to connect the signal_detect signal of PCSPMA GTP core to indicate presence of optical input? ... water9580

ML555 SATA GTP dosen't work 2 121 (7/6/2007 4:19:48 PM) comp.arch.fpga My SATA host controller includes TX/RX OOB Sequence generation ciruit(it can generate COMRESET/COMINIT/COMWAKE). My GTP setting is as following, a>GTP clock:150M,Gen1 mode,8 GTP; b>Datawidth:16bit,enabl... water9580

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frame value too large by ifconfig!!!! 4 25 (2/24/2008 2:49:10 AM) comp.os.linux.networking my NIC doesn't work .My os is RHEL5.1/32bit/dual core intel cpu. the ifconfig output: eth2 Link encap:Ethernet HWaddr 00:55:7B:B5:7D:F7 inet addr:192.168.1.22 Bcast:192.168.1.255 Mask:255.255.255.0 inet6 addr:... water9580 (83)

LS & MMSE channel estimators for OFDM 2 45 (5/12/2006 2:16:02 PM) comp.dsp http://www.rdfwt.com/showthread.php?p=500#post500 ... water9580 (83)

OFDM Transceiver code #2 7 52 (4/13/2006 6:14:55 AM) comp.dsp This code was used for making the practical measurements in section 2.3 of my thesis. This Matlab code allows an OFDM signal to be generated based on an input data file. The data can be random data, a grey scal... water9580 (83)

Hello,you can browse the contents after activating your register account 3 41 (3/30/2006 4:44:58 AM) comp.arch.embedded www.buswares.com--discuss computer and communication bus www.rdfwt.com--discuss wireless technology ... water9580 (83)