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How to detect a combinational feedback loop

Hello, experts!


Can somebody advice me how to detect _combinational feedback loops_ in
the design? Is there any tool that can catch path through which such
feedback is propagated? Maybe, some synthesizer can highlight such
loop on the generated schematic drawing?


Thanks in advance!
-dmitriym

0
dmitriym
4/28/2007 3:54:17 PM
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On Apr 28, 11:54 am, dmitriym <explo...@inbox.ru> wrote:
> Hello, experts!
>
> Can somebody advice me how to detect _combinational feedback loops_ in
> the design? Is there any tool that can catch path through which such
> feedback is propagated? Maybe, some synthesizer can highlight such
> loop on the generated schematic drawing?
>
> Thanks in advance!
> -dmitriym

Synopsys Design Compiler does it with report_loops" command on already
synthesised designs.
Probably, other synthesis tools can do the same.

Also, most of LINT tools (such as Synopsys LEAD) can find loops in
RTL  much quicker.

And finally, simulators such as Modelsim report about combinational
loops (oscilations) during 0-delay gatelevel simulation.

-Alex

0
Alex
4/28/2007 8:22:03 PM
On 28 ���, 23:22, Alex <agnu...@gmail.com> wrote:
> On Apr 28, 11:54 am, dmitriym <explo...@inbox.ru> wrote:
>
> > Hello, experts!
>
> > Can somebody advice me how to detect _combinational feedback loops_ in
> > the design? Is there any tool that can catch path through which such
> > feedback is propagated? Maybe, some synthesizer can highlight such
> > loop on the generated schematic drawing?
>
> > Thanks in advance!
> > -dmitriym
>
> Synopsys Design Compiler does it with report_loops" command on already
> synthesised designs.
> Probably, other synthesis tools can do the same.
>
> Also, most of LINT tools (such as Synopsys LEAD) can find loops in
> RTL  much quicker.
>
> And finally, simulators such as Modelsim report about combinational
> loops (oscilations) during 0-delay gatelevel simulation.
>
> -Alex

Hello, Alex!

Thanks a lot for your reply!
You've really helped me: I'll try the "reply_loops" command for the
Design Compiler! I guess, it should help.

PS: I've tried the LEDA - it reports only "loop is detected" (it
doesn't report any propagation path). Maybe I've an old version of
this tool...

Regards,
dmitriym

0
dmitriym
4/29/2007 8:07:48 AM
Synopsys VCS can also help you in this requirement.

[1] You can try to compile the test case using +vcs+loopreport compile
time switch. Then run the simv using +vcs+loopreport. You may see loop
report.

[2] Please use the option +vcs+loopdetect along with your compilation
command.

        %> vcs +vcs+loopdetect ...[other_options]
 >> This directly gives you the loop info.

--Karthik

0
karthik
4/29/2007 11:03:42 AM
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